NuFront

"Timing Closure is the most critical stage for our SoC implementation We needed to fix complex timing issues fo...

HLMC

"Tapeout is one of the major functions that a design support team handles It requires engineers to review custo...

ZTE

" Our SoC designs in 40nm have complex clock scheme Some of the clock frequency is over 1Ghz We have adopted...

HiSilicon

"Practically speaking, every SOC design closure takes not only a significant amount of time and effort, but multi...

MPS

"Over the last two years, we have successfully used multiple analog mixed-signal IC tools such asAeolus,Aetherandiwa...

iWatt

" Interconnect extraction and analysis has always been a bottleneck in our design flow, and is becoming a critic...

HHGrace

Empyrean’s ALPS™ reduces the simulation time for IP designs significantly and provides accuracy that can...