As IC design and manufacturing technology process shrink down, layout design data scale has become enormous. Engineers in FAB need to view large amount of layout data every day. Besides, merging silicon-proven IP with customer’s design, confirming the layout differences for different design version, reporting DRC/LVS violations and discrepancies are also part of onerous daily work.
Empyrean provides a total solution for viewing layout and mask data. Supporting GDS/OASIS/MEBES/JDV format, multiple IP Merge/Cell Switch mode, built-in the fastest layout-to-layout comparison, versatile DRC/LVS back-annotation and snap shot function, these helps FAB engineers relieve the heavy workload, and makes tape-out deliver on time.
Standard Cell/IP Design ---- Aether
Aether is Analog/Customl IC design platform, including schematic and layout design of the standard cell library/IP. Empyrean’s SPICE simulator-ALPS-AS and physical verification tool-Argus can be integrated into Aether platform. The popular third-party tools also can be integrated . So the design flow is very smooth and efficient.
Standard Cell/IP Simulator ---- ALPS-AS/iWave
ALPS-AS is a highly accurate, transistor-level, parallel mode circuit simulator which support SPICE simulation for standard cell andIP module ; Base on the unique RC reduction and parallel mode simulation technology, it can beat the full chip of IP design post-simulation for deep sub-micron and nanometer process effectively . iWave is a high performance mixed-signal waveform display and analysis tools. It supports all popular waveform formats and makes the post-processing of the data conveniently, such as the operations of measurement and calculation.
Standard Cell/IP Verification ---- Argus/FlashLVL/PVE
Argus offers fast and easy-to-use DRC/LVS debugging capabilities using PVE (Physical Verification Environment). Capabilities include back-annotation, sorting, querying, violation-waiver, rule-deck editing, net tracing, short-locator, cross-probing between layout and schematic, extract logic-views from layout and source netlists. Argus provides both GUI mode and batch mode execution with seamless integration to leading layout tools.
IP Merge ---- Skipper
Skipper is a powerful and extremely fast chip-finishing layout platform for ultra large scale chip designs. It can display, check and edit layout. It combines an optimized database and highly effective memory management. It can handle large designs with 100GB GDS data and performs fast data convert/export, compare, edit/search operations with relatively small system resources, greatly reducing update time. For large SoC design, especially in the chip assembly and sign-off stage,Skipper offers the performance, capacity and the right capabilities to accelerate tape-out closure.
SmartMemory Compiler Builder (SMCB) is an interactive Memory-Compiler generation platform. With SMCB, user can develop the own Memory-Compiler based on specified layout tiling rule, netlist tiling rule and critical path, and then auto generates Verilog, CDL, GDS, LEF, LIB and Datasheet for compiled memory. Since SMCB released, many foundries and design houses in China, Japan and USA, have used SMCB for their own Memory-Compiler development, including single-port SRAM, dual-port SRAM, ROM, Register File and Customized Architecture Memory IPs from 130nm to 28nm.