The TSMC 2018 North America OIP Ecosystem Forum will take place on October 3rd, Wednesday, at Santa Clara Convention Center.  We cordially invite you to visit our booth #503 to see how Empyrean tools can help your clock design and chip performance.

Empyrean provides quality solutions to enhance PPA, improve yield and reduce TAT will highlight technology breakthroughs in True-Spice circuit simulation; Clock Tree analysis, constraint validation and optimization; high speed high capacity GDSII/OASIS analysis; and Lib/IP validation & QA.  Here are some product highlights:

 

Empyrean ALPS™

  •     True SPICE parallel circuit simulator, boosted by smart matrix solver technology, 5-10X speed up for post-layout simulation, top-choice for applications requiring high accuracy and quick TAT

Clock Explorer™

  •     CTS analysis and diagnostic platform facilitating efficient collaboration between front end and back end design teams to significantly reduce CTS iterations

Skipper®

  •      Large scale layout data processing platform. Speedup the process of chip finishing and chip failure analysis.

Please contact us at info@empyrean-tech.com to arrange for a private presentation of products and capabilities. Looking forward to seeing you at TSMC 2018 OIP at Santa Clara!

 

 

Venue: Santa Clara Convention Center
Date: Wednesday, October 3rd, 2018
Time: 8:30am to 6:30pm