As technology nodes move into advanced process, the SoC design scale and complexity increase rapidly. The impact of clock network on the quality of the entire design increases. Problems on the clock can lead to project delay, chip revision, and loss of yield. Front/middle-end design engineers must tackle problems with clock network and constraints prior to RTL codes sdc signoff. Back-end design engineers, in order to reduce CTS design cycle, must optimize CTS strategies by checking the physical placement of the clock network and analyzing clock structure. To avoid undesired CTS results, the bottleneck identification and modification need to be done before a new iteration. All these require designers lots of effort and years of experience.
Empyrean ClockExplorer, a dedicated clock analysis and diagnosis platform, is designed to solve clock design difficulties in each stage, reduce clock design cycle and get better CTS results. It has powerful clock schematic viewer to help designers sort out clock tree structures and develop better CTS strategies. The rule-based clock checks help designers evaluate the quality of clock design, find out bottlenecks and improve CTS quality.