Timing closure is a major challenge for SoC designs, affecting both design quality and time to market. While dealing with huge timing data and making an optimization plan in a tight schedule, timing closure is a huge difficulty, especially in the advanced process.
ICExplorer-XTop provides a comprehensive timing closure solution. It can fix timing violations such as setup, hold, transition and leakage power in super large scale, multi-scenario, advanced node designs.
ICExplorer-XTop also has post-mask ECO, interactive ECO, and clock ECO to fix timing in the critical path and improve the efficiency of timing closure.