As technology nodes move into 16nm and below, the SoC design scale and complexity increase rapidly. It requires designers to spend longer time to analyze and optimize complex clock network. Timing closure becomes a major challenge for SoC design, affecting both design quality and time to market. Advanced node design’s pursuit of ultra-low supply voltage is challenging the traditional timing sign-off solution. It also creates new challenges for library analysis and quality assurance. The GDS layout size can be more than 1TB, making it almost impossible for even reviewing and integrating the layout.

Empyrean provides several point tools for SoC design optimization such as Qualib®, ClockExplorer®, Empyrean XTop™, Empyrean XTime™ and Skipper®. Verified by 7/7+nm processes, our SoC products help users improve their productivity and reduce design cycle. With more than 100 customers worldwide, our SoC solutions have been adopted by many top SoC design companies such as UNISOC, Marvell, TSMC, SMIC, YMTC, NVIDIA, XILINX, SanDisk and Samsung.