With the process nodes of chip design and manufacture moving towards nanometer scale, the function of chip becomes more and more complex, foundries are facing more and more challenge to deliver process data and chips with high yields, such as frequently library updating, customization, larger scale of layout data, various IP merging for different customers, time-consuming DRC/LVS report preparation and yield and reliability analysis. Empyrean proposes the following efficient and accurate solutions which are close to foundry application habits to ensure the smooth delivery of tape-out.
Standard Cell/IP Design-Empyrean Aether™
Empyrean Aether™ delivers a complete and integrated solution for schematic and layout designs of standard cell and IP. Empyrean Aether™ seamlessly integrates Empyrean ALPS™ SPICE simulator, Empyrean Argus™ physical verification tool, and Empyrean RCExplorer™ parasitic RC extraction tool and other mainstream third-party tools.
Standard Cell/IP Simulation—Empyrean ALPS™
ALPS is the next-generation high-performance high-accuracy true SPICE simulator. Standard cell characterization and spice simulation of IP designs are the main application of ALPS in the foundry. ALPS proprietary Smart Matrix Solving technology provides efficient matrix preconditioning to enable faster convergence and faster post layout than other parallel SPICE simulators.
Standard Cell/IP Verification—Empyrean Argus™/Empyrean RCExplorer™
Empyrean Argus™ is an accurate and fast physical verification tool system with various applications such as DRC/LVS/LVL/ERC. The tools can be easily integrated into the Empyrean Aether™ IC design platform, Skipper® platform, and other mainstream IC design platforms. Empyrean RCExplorer™ can either perform the parasitic extraction for the standard cell design or come with Empyrean Argus™ LVS or third party LVS tools to extract parasitic at the transistor level.
Chip Finishing Platform—Skipper®
Skipper® is an efficient easy-to-use layout analysis and integration tool; handling up to 1TB size layout data with fast visualization while generating the smallest memory footprint. It also provides Foundry with a series of convenient operations such as FIB, process migration, IP Merge, layout marking, and editing.
Standard Cell/IP Analysis and Validation—Qualib®
Qualib® provides a comprehensive platform for IP, standard cell and memory library analysis and qualification. It helps the designers to perform quality checking, library PPA (Performance, Power and Area) comparison, PPA trend analysis, dynamic timing validation via SPICE simulation, and IP missing ARC validation using AI technology.
SPICE-Accurate Timing Analysis—Empyrean XTime™
Empyrean XTime™ provides a timing-based SPICE accurate process analysis solution, to perfectly solve the accuracy problem between STA and silicon for advanced process nodes, 16-nm and beyond. It can help Foundry to build up the Ring Oscillator flow for process analysis easily. The built-in V/T sweep function automatically analyzes the sensitivity of timing paths to voltage and temperature variation. Fast Monte-Carlo simulations provide an efficient and accurate process variation analysis. If the process result is not as good as expected, XTime can provide guidance for process optimization.