Job Number: DaV 31902
Position: Application Engineer
Location: San Jose, CA
Job Duties and Responsibilities:
This position serves as EDA (Electronic design automation) tools technical support to customers. This position will work with customers and assist to create solution for the problems that customers encounter when using our EDA tools. The major duties are:
- Provide pre- and post-sales technical support for SoC (System-On-Chip) and Mix-signal design products. Prepares and delivers technical presentation and explaining products to the users and prospective customers.
- Conduct software evaluations, benchmarks, and product presentations, and develops and integrates tool flows into customer design environments with application of SoC digital physical design flow.
- Articulate customer issues and requirements to the Research & Development team and provides solutions to customers and technical guidance to product engineering by applying expertise in physical design and optimization such as placement, routing, cell sizing, buffering etc. to improve timing and power requirements.
- Document solutions, and prepares application notes and provides training and tool support to the users.
- Perform clock analysis, CTS (Clock Tree Synthesis) including concurrent clock optimization, solve problems on complex CTS (clock tree synthesis).
- Perform digital implementation through ECOs, physical design and optimization to improve timing and power designs.
The candidate will take charges of SoC (System-on-Chip) products which include four main kinds of tools, including the timing closure tool, clock tree analysis and optimization tool, chip layout finishing tool and standard cell/IP quality check tool. To perform this job successfully, an individual must be able to perform each essential duty satisfactorily.
- Bachelor’s degree in EE is required, Master degree is preferred.
- Excellent knowledge of SoC digital physical design, having at least 6 years digital physical implementation experience. Expertise in all the tasks on digital physical design and optimization from RTL to GDSII, which include synthesis, floorplan, power planning, clock tree synthesis and optimization (including concurrent clock optimization), logic restructuring, place and route, RC extraction, static timing analysis, cross talk/ noise analysis, power analysis, rail analysis (IR, EM), physical aware timing ECO and functional ECO, chip finishing and physical verification.
- Expertise in digital blocks integration and physical verification by mainstream EDA tools like Cadence Virtuosos and Mentor Calibre/Calibre-DRV.
- Having strong knowledge in clock analysis, CTS including concurrent clock optimization. Can solve problems on complex clock tree synthesis.
- 3+ years’ experience in digital frontend design and simulation and verification, standard cell library development, prepared different kind of models for implementation usage.
- Expertise in Makefile/Perl/Tcl programs.
- Excellent communication skills.
Medical, Dental and Vision insurance plans, FSA plan, Paid time off, 401K, Team building events, etc.
Job Type: Full-time