Empyrean EplantFPD™ is a toolset used for full panel layout analysis. It includes IRdrop, EM, and post-simulation debug analyses, which are based on accurate 3D RC extraction.
- EplantFPD IRdrop: for a high-resolution panel, the IRdrop tool is used to simulate the voltage distribution of the power and ground nets in the full panel. It is critical for optimizing the panel design
- Array mode extracts accurate resistance;
- Cascade mode outputs panel netlist;
- Calculates voltage distribution for nets based on the voltage of port node in hierarchy mode-shown by the usage flow;
- Integrated viewer smoothly displays voltage distribution for users to view and optimize a design.
- EplantFPD EM: EM analysis by simulating current distribution is critical for optimizing panel designs used for high-resolution display.
- It generates hierarchical resistance network;
- Calculates current density distribution based on the distribution of node voltages and meshes;
- Integrated results viewer shows current direction, current density, and current density distribution, enabling a user to better optimize the design.
- EplantFPD Debug: panel level post-simulation analysis tool for debugging layout and parasitics for OLED pixel and GOA peripheral circuit layout.
- Highly accurate 3D RC extraction;
- Supports automatic port generation based on a circuit schematic, layout signal ports, and design pattern. In addition, it can also automatically export the corresponding netlist file;
- Generates DSPF file with 3D RC geometry information and offers DSPF file analysis including pin to pin wire resistance, coupling capacitance for all signals, and detailed capacitance data for specified signals;
- Supports RC back annotation on to layout.
- Allows high-resolution full panel IRdrop analysis through highly accurate 3D model-based extracted RC netlist
- Allows fast visualization of full panel IRdrop and EM distribution
- Multi-threading operation for faster design performance and efficiency
- Seamlessly embedded in AetherFPD tool
- Allows efficient post-simulation debug and design optimization