ClockExplorer®
In today’s advanced designs, with the number of clocks and domains growing rapidly, the complexity of clock analysis and optimization has exploded. Typically, a front-end team generates clock constraints which are seldom CTS-aware, resulting in higher clock latency and buffer count.ClockExplorer provides a platform for both front-end and back-end teams. It provides comprehensive clock check within a KPI (Key Performance Indicator) system, which help designer review the clock structure, ensure and improve the CTS quality.
- Front-end: Validate and sign-off SDC and clock design using comprehensive clock analysis
- Back-end: Analyze, optimize and generate constraints for better CTS
Key Features
- One-click clock analysis and diagnosis platform with KPI (Key Performance Indicator)
- Powerful clock schematic and cone schematic display
- Comprehensive clock design check for both preCTS and postCTS stage
- Clock constraint generation for better CTS strategy
Benefits
- Quickly have a clear understanding of clock structure
- Effective to get better CTS strategy for higher clock synthesis quality
- Easy to know bottleneck of CTS result and reduce clock design cycle
- Lowers design power and clock OCV
- Accelerates timing closure process