At 16nm and below advanced process nodes, traditional corner-based timing sign-off method is facing great challenges. Process effects, like the Miller Effect and the Long Tail Effect, have a serious impact on timing performance, resulting in a larger discrepancy between the STA calculation and the actual silicon measurement. For low voltage design, dynamic voltage and frequency scaling (DVFS) scheme are not enough, since foundries provide a limited number of process corners to model process variation. Therefore, a new solution is needed to analyze the performance of the design across the entire PVT and RC variation. Advanced process node’s non-Gaussian distribution of process variations is even worse at low voltages. Although STA tools have incorporated more sophisticated models such as AOCV/POCV/LVF to characterize variation effects, they will cause excessive pessimism or incomplete coverage. Considering variation’s effect on reliability, designers need to find a more potent solution.
Empyrean XTime™ provides SPICE accuracy and fast timing analysis solution, to fill the gap between STA and silicon for advanced process nodes, especially for low-voltage IoT designs. The built-in V/T sweep function automatically analyzes the sensitivity of timing paths to voltage and temperature variations. Lighting fast Monte Carlo simulations provide efficient and accurate process variation analysis. The Aging simulation covers dynamic effects for reliability analysis.
XTime has been adopted by many chip design companies for timing verification, variable voltage performance prediction, timing signoff criteria formulation, and dynamic effects analysis. The design types include CPU, bitcoin mining, IoT, mobile phone, network, etc. Verified by post-silicon measurement, the data correlation with silicon is within ±2%.