Timing arcs in AMS IPs are typically determined manually using spreadsheets. Apart from the process being error-prone, it relies on the designer’s expertise to not miss an arc. In addition, IPs get integrated into many applications beyond what an IP designer designed it for. Working reliably across those applications is mandatory, and that from a timing point of view calls for the most complete modeling of timing arcs. Current process for AMS IP’s is manual and error-prone with the potential for many missed arcs – a liability for SoCs that use such IP’s!
The webinar will focus on a new AI-powered automated timing arc prediction and validation capability, the first commercial capability of its kind for AMS IP’s. It automates the otherwise manual task and reduces the risk of delayed tape-out or multiple silicon iterations.
A joint paper was presented by a major customer of ours at the 2019 DAC as mentioned in the following link: (http://www2.dac.com/events/eventdetails.aspx?id=268-123).