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Digital SoC Design Solution

Empyrean Technology provides a set of SoC solutions including standard cell library characterization, memory characterization, mixed-signal IP characterization, standard cell library and IP validation, clock diagnosis and analysis, accurate timing simulation and analysis, timing and power optimization, layout integration and analysis, digital physical verification and parasitic RC extraction.

  • Empyrean Liberal™ provides a solution for quality sign-off standard cell library characterization.
  • Empyrean Liberal-Mem™ and Empyrean Liberal-IP™ use a combination of static analysis and dynamic simulation for characterization of timing model. Compared with the conventional method of timing model characterization extraction based on full process circuit simulation, it achieves a speedup of more than 10 times and improves design efficiency.
  • Empyrean Qualib® provides analysis and validation on standard cell library and IPs among various design views to ensure design quality.
  • ICExplorer-XTime™ provides a highly accurate timing analysis solution for designs in advanced and low-voltage designs. It provides a more efficient solution to the challenge of timing and design reliability for advanced and low-voltage designs.
  • ICExplorer-XTop™ provides timing and power optimization for advanced processes, large-scale and multi-scenario timing closures, including setup, hold, transition time, leakage and dynamic power optimization.
  • Empyrean Skipper® provides layout integration and analysis for ultra-large-scale layout, including fast loading and viewing of ultra-large-scale layout, fast layout integration, batch processing for layout, multi-threaded net tracing and point-to-point resistance analysis. It provides an efficient analysis and data processing solution for ultra-large-scale layout.
  • Empyrean Argus™ is a digital physical verification tool. It is a hierarchical and parallel physical verification tool for ultra-large-scale layout design and development. It can quickly, accurately and comprehensively conduct physical verification for ultra-large-scale layout that significantly improves the efficiency of designers in verifying and analyzing layout design errors.
  • Empyrean RCExplorer™ is a digital parasitic RC extraction tool. It uses multi-threading and multi-machine parallelism, and realizes rapid extraction of high-precision parasitic parameters for digital ultra-large-scale layouts.

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