Product Portfolio
Current location:Home page > Product Portfolio > AMS and PMIC Design and Verification Platform > Empyrean Ada™ – Layout Parasitic Analysis
Empyrean Ada™ – Layout Parasitic Analysis

Fast DSPF-Based RC Analysis

 


 

Shrinking process geometries, along with the adoption of new device structures and the increasing number of metal layers, have introduced new parasitic effects into IC designs, adding considerable verification complexity and simulation time.  Designers need a fast and accurate solution to effectively analyze these effects and accelerate design closure. 
 

Empyrean Ada™ provides high-performance RC analysis for efficient layout optimization. Leveraging its large-capacity database, multi-threading technology, and seamless back-annotation capabilities with Empyrean Skipper®, Ada delivers fast and accurate parasitic analysis through both batch and GUI-based workflows for maximum ease of use.
 

Key capabilities include Net RC analysis, Net RC comparison, node-to-node resistance analysis, cross-coupling analysis, and advanced P2PR analysis.
 

Key Benefits:  Quick Optimization to Locate Critical Nets
 High Performance - Next-Generation database architecture with advanced multi-threading capabilities 
 High Efficiency - Fast analysis of parasitic resistance and capacitance
 Ease of Use - Seamless GUI and back-annotation capabilities enable interactive result viewing with Aether and Skipper

 

© 2024 Empyrean Technology Co., Ltd  www.empyrean-tech.com