Achieving the required performance using the lowest possible power is critical for every SoC design. Making sure the closure on performance and power are achieved in a time-frame as determined by market is key for success of a chip.
Empyrean Software offers a complete Analog and Mixed-Signal design solution with a competitive set of tools that covers schematic/layout (Aether), circuit simulation(ALPS), and physical verification (Argus).
IP & Design Service
We offers high performance and low power interface IPs that has been proved in major foundries with the process 350nm to 28nm, and also offers IPs for SoC platforms like multimedia (Audio / Video) and Internet of Things (IoT) to achieve recent design demands.
“Benefiting from abundant experiences and test data, MPS has been leading the CMOS power supply technology in the world, With help from Empyrean’s Polas power layout analysis solution, we were able to analyze and build the required reliability into the design prior to tape out. We also chose Empyrean for their excellent support on a variety of customized features. ”Zhengwei Zhang, Vice President of Design Engineering at Monolithic Power Systems, Inc.
“During chip finishing time, short-debugging is always a painful exercise for us. With Empyrean’s SkipperTM, our engineers could easily and quickly locate and pinpoint the shorts on the layout. Mixed signal designs usually take a long time to simulate because we have to flatten the digital blocks into transistor level blocks first and use SPICE simulator for the simulation. With Empyrean ALPSTM we can finish simulation multiple times faster than our existing solutions.”Andy Tsong, Division Manager of Diodes Incorporated
“It was necessary to build a smooth mixed-signal IC design flow with a one-stop platform to bring our design method to the next level. With the help of TowerJazz’s iPDK and Empyrean’s AMS flow, a high degree of automation flow has been made possible. We also chose Empyrean for their ability to provide us excellent support all over the world.”Guoxing Li, VP of O2Micro Inc.
“Recent advanced designs have complicated clock structures to achieve higher performance and lower power consumption, which makes it hard to detect the clock problems in a short period of time. ClockExplorer can help to report Clock KPI in various design stages such as pre-Place, pre-CTS, and post-CTS, with helpful numerical scores to indicate the quality of clock structure. This has enabled us to avoid issues that could have arisen in the later stages and enhance our product quality.”Kazuhiro Takahashi, Senior Principal Engineer of the Digital Design Technology Department, Shared R&D Division 2, Broad-based Solution Business Unit at Renesas Electronics Corporation.