Article originally published on Semiwiki.com, "Viewing the Largest IC Layout Files Quickly" Wrote by Daniel ...
Empyrean Polas™ Empowers a High-Performance Power IC Provider to Build-in Reliability Prior to Tape-out
SANTA CLARA, Calif. –– Aug 2nd, 2019 –– Empyrean Software (Empyrean) today announced that Monolithic ...
What Clients Say?
“During chip finishing time, short-debugging is always a painful exercise for us. With Empyrean’s Skipper®, our engineers could easily and quickly locate and pinpoint the shorts on the layout. Mixed-signal designs usually take a long time to simulate because we have to flatten the digital blocks into transistor-level blocks first and use SPICE simulator for the simulation. With Empyrean ALPSTM we can finish simulation multiple times faster than our existing solutions.”
“Recent advanced designs have complicated clock structures to achieve higher performance and lower power consumption, which makes it hard to detect the clock problems in a short period of time. ClockExplorer can help to report Clock KPI in various design stages such as pre-Place, pre-CTS, and post-CTS, with helpful numerical scores to indicate the quality of clock structure. This has enabled us to avoid issues that could have arisen in the later stages and enhance our product quality.”
“It was necessary to build a smooth mixed-signal IC design flow with a one-stop platform to bring our design method to the next level, With the help of TowerJazz’s iPDK and Empyrean’s AMS flow, a high degree of automation flow has been made possible. We also chose Empyrean for their ability to provide us excellent support all over the world.”
“Benefiting from abundant experiences and test data, MPS has been leading the CMOS power supply technology in the world, With help from Empyrean’s Polas power layout analysis solution, we were able to analyze and build the required reliability into the design prior to tape out. We also chose Empyrean for their excellent support on a variety of customized features. ”