Reliability Analysis for Power IC Designs

Simulating the working state of power ICs accurately to improve reliability and yield is a difficult problem for power IC designers.

Traditional RC extraction methods cannot satisfy power IC design needs because power ICs often use special shapes and have large areas. Sometimes their layout satisfies DRC/LVS rules but they still may not function correctly. Traditional RC extraction often requires long run times for accurate power and current simulations, leading to extended analysis and debugging cycles. As a result, it is difficult to predict the performance and reliability of power ICs which leads to higher design risk and longer product development cycles.

Empyrean Polas™ is an effective and one-stop solution for power IC analysis, and it allows designers to sign off and safeguard the quality of their designs. The highly integrated solution includes LVS, RC extraction, simulation, results view, and results analysis. Key technologies  include a field solver for handling special polygons, which improves the extraction accuracy over traditional polygon-based methods, and long-channel break down to build correct current flow path.
 

Key Benefits
High Accuracy for Power IC Signoff
 Efficient 3D field solver - Accurately handling special shapes and large areas of PMIC  designs
 Comprehensive Analysis - Include accurate Rds(on) calculation, EMIR analysis, power MOS
           timing analysis, RMAP analysis, etc
 Complete System - Highly integrated system, including LVS, Extraction, Simulation, Results
           View, and Results Analysis