High-performance Physical Verification Signoff Solution

Empyrean Argus™ is a hierarchical and parallel physical verification tool that meets the requirements of ultra-deep submicron IC designs.

Empyrean Argus™ can be seamlessly integrated with Empyrean Aether™, an analog circuit schematic and layout design platform, and Empyrean Skipper^®, a massive layout processing platform.  It helps layout engineers quickly locate layout design errors, speed up the verification process, and shorten the product development cycle through its intuitive debugging capabilities.

Empyrean Argus™ is widely supported by leading foundries worldwide, providing designers with signoff-quality verification.
 

Key Benefits:  Signoff-Quality Verification Accuracy
 High Performance – A new-generation hierarchical parallel physical verification solution for nanoscale IC designs
 High Accuracy – Layout preprocessing detects and resolves design errors early in the design cycle, ensuring signoff-quality accuracy without sacrificing performance 
 Ease of Use – DRStudio streamlines rule development, while comprehensive debugging functionalities improve efficiency and productivity