Empyrean Qualib

Empyrean Qualib® provides a comprehensive analysis and validation platform for standard cell libraries and IPs. It offers PPA (Performance, Power, and Area) comparison and trend analysis across different library releases/revisions, dynamic timing validation through SPICE simulation, and AI-powered validation of missing IP timing arcs.  These capabilities help designers perform library quality inspections more efficiently.

Empyrean Qualib® supports a wide range of process nodes and design types, including standard cell libraries, Memories, I/Os, and analog IPs.  It also supports various library views and design data formats, such as GDSII/OASIS, Verilog, Liberty, and LEF.  In addition, Liberty APIs enable detailed and customized timing data verification and analysis.

With its user-friendly GUI, high-performance architecture, comprehensive inspection reports, and advanced analysis capabilities, Qualib® significantly reduces verification iterations, ensures design quality, and shortens time-to-market.