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Digital SoC Design Solution

Empyrean Technology provides a series of SoC solution including standard cell library characterization, standard cell library and IP validation, clock diagnosis and analysis, accurate timing simulation and analysis, timing and power optimization, and layout integration and analysis.

  • Empyrean Liberal provides a solution for sign-off quality standard cell library characterization.
  • Empyrean Qualib provides analysis and validation on standard cell library and IP to ensure design quality.
  • Empyrean ClockExplorer provides clock diagnosis and analysis to reduces design reduce iterations and improves design cycles.
  • ICExplorer-XTime provides a high accuracy timing analysis solution for advanced process and low voltage design. It brings a more efficient solution to the challenge of timing and design reliability in the advanced process and low voltage design.
  • ICExplorer-XTop provides timing and power optimization for advanced process, large-scale and multi-scenario timing closures, including setup, hold, transition and leakage power optimization.
  • Empyrean Skipper provides layout integration and analysis for ultra large scale layout, including fast loading and viewing of ultra large scale layout, fast layout integration, batch processing for layout, multi-threaded net tracing and point-to-point resistance analysis. It brings an efficient analysis and data processing solution to the ultra large-scale layout.




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