Empyrean Technology offers a comprehensive suite of SoC design solutions, covering standard cell library characterization, memory characterization, mixed-signal IP characterization, standard cell library and IP validation, clock diagnosis and analysis, accurate timing simulation and analysis, timing and power optimization, layout integration and analysis, digital physical verification, and parasitic RC extraction.

Library characterization and validation solutions for standard cell libraries, memories, and mixed-signal IPs:

• Empyrean Liberal™ provides a comprehensive solution for sign-off quality standard cell library characterization.

  • Empyrean Liberal-Mem™ and Empyrean Liberal-IP™ leverage a combination of static analysis and dynamic simulation technologies for timing model characterization. Compared with conventional characterization methods that rely on full-process circuit simulation, they deliver a 10x speedup, enabling substantially improving design productivity.

• Empyrean Qualib^® provides comprehensive analysis and validation across multiple design views for standard cell libraries and IPs, ensuring design accuracy and quality.

Clock diagnosis and analysis, accurate timing simulation and analysis, and timing and power optimization:

• ICExplorer-XTop™ delivers an advanced timing and power optimization solution for large-scale designs, cutting-edge processes, and multi-scenario timing closure challenges.  It enables efficient optimization of setup, hold, transition timing, as well as leakage and dynamic power, helping designers achieve faster convegence.

• ICExplorer-XTime™ provides a highly accurate timing simulation and analysis solution for advanced-node and low-voltage designs. It addresses the limitations of accurately evaluating timing behavior and design reliability using conventional static timing analysis (STA).

Data integration and analysis, physical verification, and parasitic RC extraction for ultra-large-scale layout designs:

• Empyrean Skipper^® is a high-performance layout data processing and analysis solution featuring rapid layout loading and viewing, layout integration, batch processing, multi-threaded net tracing, and point-to-point resistance analysis.

• Empyrean Argus™ leverages hierarchical architecture and highly scalable parallel processing to deliver industry-leading performance for physical verification.

• Empyrean RCExplorer™ provides fast and accurate parasitic RC extraction through advanced multi-threading and distributed computing technologies, helping designers shorten turnaround time and achieve signoff confidence.