Empyrean Skipper

As process technologies advance and design complexity continues to increase, chip sizes are growing rapidly. Some designs exceed 400 mm² and incorporate more than 10 billion transistors. These ultra-large-scale designs place stringent demands on layout tools in terms of data loading and storage performance, layout integration, querying efficiency, and overall design productivity.

Empyrean Skipper® provides a powerful layout analysis and integration solution for improving layout signoff efficiency. Innovative cache and shared-memory technologies deliver industry-leading performance and significantly reduce layout loading time.  Its parallel layout scanning technology further accelerates IP integration and merging for large-scale designs.

Empyrean Skipper® offers powerful chip-level layout analysis in a user-friendly environment, including:

• Net and short tracing
• Layout comparison
• Point-to-point (P2P) reliability analysis
• Weak connectivity analysis
• Density checking
• Pad reporting

It also provides intuitive debugging and review features for LVS and DRC violations, support for FIB processing workflows, and unique digital signature tracking technology for efficient IP management and traceability.  Skipper supports a wide range of industry-standard data formats, including GDS, GDS.gz, OASIS, LEF/DEF, and MEBES.