The verification of analog design is becoming extremely important at an advanced node, but it’s too much time-consuming in post-layout simulation because of a more complex device model, exponentially growing parasitics and much more signoff corners. It often takes months, even longer for millions of statistical simulations to run. Traditional simulation and verification tools have been unable to meet the development requirements of circuit design. The traditional SPICE simulator based on CPU architecture can not significantly improve the simulation performance because of the constraints of CPU’s computational power and concurrency mechanism. A new architecture is urgently needed to break through the simulation bottleneck.
Empyrean ALPS-GT™ is a heterogeneous simulation system based on CPU-GPU platform architecture. Compared with CPU architecture, it provides more than 15X computing resource and greatly improves the performance with GPU-Turbo Smart Matrix Solving (SMS-GT) technology. It delivers 100% SPICE accuracy and breaks through large-scale analog circuit simulation performance bottleneck, and achieves 10+X performance speedup than the current CPU-based parallel SPICE for post-layout circuit simulation.