Timing closure is a major challenge for SoC designs, affecting both design quality and time to market. In advanced process nodes, large designs typically contain more than 100M instances and hundreds of scenarios. Timing closure, while dealing with huge timing data and making an optimization plan in a tight schedule is a huge challenge, and even more so at 16nm and below. Automatic timing optimization cannot solve all timing problems. Designers are forced to spend lots of time implementing appropriate ECOs manually.
Empyrean XTop™ provides a fast, high capacity, and comprehensive ECO closure solution. It can fix timing violations in super large scale, multi-scenario, advanced node designs. XTop also provides an interactive ECO solution. Through analyzing and locating the bottleneck problem, designers can manually fix critical timing paths, greatly improving the efficiency of timing closure.
XTop has been adopted by leading IC design companies as their sign-off timing closure solution and has delivered hundreds of successful tape-outs. XTop supports 16/14/10/7nm process nodes and used in a variety of design types, such as mobile, PCs, servers, networks, media, IoT (Internet of things), mining machines, etc.