Empyrean ArgusFPD™

Empyrean ArgusFPD™ allows you to comprehensively check the physical and electrical integrity of FPD designs, using the built-in DRC, LVS, and related utilities. ArgusFPD is seamlessly integrated to AetherFPD allowing effective detection of design violations, reducing verification time and improving productivity.

  • ArgusFPD DRC (Design Rules Check): performs comprehensive design rule checking of flat and hierarchical layout in multithreaded configurations meeting high performance, capacity and precision. Also, ArgusFPD DRC can perform checking of specific regions or selected rule checks including width, space, overlap, and antenna check.
  • ArgusFPD LVS (Layout Vs Schematic): it assists you to find mismatches between layout and schematic. Hierarchical error detection and the efficient interaction of layout, schematic and netlist, allow users to locate errors quickly and accurately.
  • ArgusFPD ERC (Electrical Rules Check): ensures the correctness of connections in an FPD design, including net open and short issues.
  • ArgusFPD LVL (Layout Vs Layout): LVL provides designers a way to find the differences between two layout databases quickly. This is very helpful in confirming a modified database. LVL can greatly improve the efficiency of confirming different layout versions.
  • ArgusFPD SVS (Schematic Vs Schematic): it is used to find the differences between two schematic databases quickly, which is helpful when a database was changed.
  • ArgusFPD DRS (Design Rule Studio): it is used to edit and check the correctness of rule-decks, debug DRC & LVS rule-decks, and more.
  • ArgusFPD PVE (Physical Verification Explorer): it is used to display, analyze and back-annotate the results to layout and schematic efficiently.
  • ArgusFPD CD(Check Density): it is used to check layer density which supports logic operation on the input layers.


  • DRS provides an integrated development environment for rule-decks​​​​​
  • Users can locate errors or violations quickly and accurately
  • PVE supports DRC/LVL result pattern
  • Supports hierarchical and flat layout verification
  • Supports interactive interface and is easy to use
  • Supports the comparison of lib before and after sizing