The parasitic effect on circuit performance becomes challenging in modern IC design, especially for 65nm and below. The accuracy of the parasitic extraction directly affects the correlation between the measured chip’s performance and post-layout simulation. Besides, the reliability-related EM/IR-drop analysis also challenges high-precision, high-speed parasitic extraction tools.
Empyrean RCExplorer™ enables to perform the parasitic extraction for the cell-level designs and transistor-level parasitic extraction by using Empyrean Argus™. RCExplorer also provides a quick analysis of point-to-point parasitic and delays based on layout and netlists. It can be widely used in layout editing, post-layout simulation debugging, PG analysis, Rds(on) analysis, and ESD analysis.
It provides users with a quick and accurate solution of parasitic analysis for design optimization.