Modern SoC designs use thousands of IPs and standard cells. The characteristics of these IPs and standard cells determine the quality of the SoC design and the design cycle. Designers need to perform an in-depth performance analysis of the IP library, verify the quality of the delivery items, and determine IP libraries suitable for the design requirements and the corresponding design rules. As process advances, the IPs become larger and more complex. Libraries have more cells, more corners, and more physical/electrical design rules. FinFET design requires even more physical constraints and reliability requirements. IoT and other ultra-low-power designs require much higher library accuracy including dynamic effects such as sensitivity. All these advances create new challenges for library analysis and quality assurance.

Qualib® provides a comprehensive platform for IP, standard cell and memory library analysis and qualification. It helps the designers to perform quality checking, library PPA (Performance, Power and Area) comparison, PPA trend analysis, dynamic timing validation via SPICE simulation, and IP missing ARC validation using AI technology.

Qualib® has improved productivity in leading IC design companies and fabs for helping the users in library validation, process library evaluation, timing calibration, and design-driven timing analysis. Some of the top design houses have been using Qualib® as their memory sign-off solution and third party IP check-in platform. Multiple leading foundries have also adopted Qualib® as part of Design Kit release sign-off solution for their IPs, Standard Cell, Memory and IO cell libraries.